View PO100HSTL179A_4566056.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PO100HSTL179A Differential LVDS/LVPECL/HSTL to LVTTL Translator LVTTL/LVCMOS to Differential HSTL Translator
FEATURES:
* Patented Technology * Differential LVDS/LVPECL/HSTL to LVTTL Translator - Operating frequency up to 1GHz with 2pf load - Operating frequency up to 800MHz with 5pf load - Operating frequency up to 450MHz with 15pf load - Very low output pin to pin skew < 150ps - Propagation delay < 1.8ns max with 15pf load * LVTTL/LVCMOS to Differential HSTL Translator - Operating frequency up to 1.65GHz with 5pf load - Operating frequency up to 500MHz with 15pf load - Very low output pin to pin skew < 100ps - Propagation delay < 1.4ns max with 15pf load * 2.4V to 3.6V power supply * Industrial temperature range: -40C to 85C * Available in 14-pin 150ml SOIC package
04/26/09
DESCRIPTION:
Potato Semiconductor's PO100HSTL179A is designed for world top performance using submicron CMOS technology to achieve 1GHz LVTTL output frequency with less than 1.8ns propagation delay and 1.65GHz HSTL output frequency with less than 1.4ns propagation delay. The PO100HSTL179A is a low-skew, The small outline 8 pin package and the low skew design to make it ideal for applications which require the translation of a clock or a data signal.
Pin Configuration
Logic Block Diagram
5 6 8 7
VCC R D GND
1 2 3 4
8 7 6 5
A B Z Y
D
3
Y Z A B
R
2
Pin Description
INPUTS VID = VA- VB VID 10 mV 10 mV < VID < 10 mV VID -10 mV Open RECEIVER OUTPUT R H ? L H INPUT D L H Open Y L H L DRIVER OUTPUTS Z H L H
1
Copyright (c) Potato Semiconductor Corporation
PO100HSTL179A Differential LVDS/LVPECL/HSTL to LVTTL Translator LVTTL/LVCMOS to Differential HSTL Translator
04/26/09
Maximum Ratings
Description Storage Temperature Operation Temperature Operation Voltage Input Voltage Output Voltage Max -65 to 150 -40 to 85 -0.5 to +4.6 -0.5 to Vcc -0.5 to Vcc+0.5 Unit C C V V V Note:
stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied.
Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input B Pullup Resistor Input A Pulldown Resistor Test Conditions Minimum Typical 4 88 88 Maximum Units pF K K
DC Electrical Characteristics
Symbol Description
Output High voltage Output Low voltage Input High voltage Input Low voltage Input High current Input Low current Clamp diode voltage
Test Conditions
Vcc=3V Vin=VIH or VIL, IOH= -12mA Vcc=3V Vin=VIH or VIL, IOH=12mA Guaranteed Logic HIGH Level (Input Pin) Guaranteed Logic LOW Level (Input Pin) Vcc = 3.6V and Vin = Vcc Vcc = 3.6V and Vin = 0V Vcc = Min. And IIN = -18mA
Min
Typ
Max
Unit
VOH VOL VIH VIL IIH IIL VIK
Notes:
1. 2. 3. 4. 5.
2.4 2 -0.5 -
3 0.3 -0.7
0.5 Vcc 0.8 1 -1 -1.2
V V V V uA uA V
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 C ambient.
This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc - 0.6V at rated current
2
Copyright (c) Potato Semiconductor Corporation
PO100HSTL179A Differential LVDS/LVPECL/HSTL to LVTTL Translator LVTTL/LVCMOS to Differential HSTL Translator
04/26/09
Power Supply Characteristics
Symbol Description
Quiescent Power Supply Current
Test Conditions (1)
Vcc=Max, Vin=Vcc or GND
Min
Typ
Max
Unit
IccQ
Notes:
1. 2. 3. 4.
-
0.1
30
uA
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
Receiver Switching Characteristics
Symbol Description
Propagation Delay D to Output pair
Test Conditions (1)
CL = 15pF 0.8V - 2.0V CL = 15pF, 125MHz CL = 15pF, 125MHz CL =15pF CL = 5pF CL = 2pF
M ax
Unit
tPD tr/tf tsk(o) tsk(pp) fmax fmax fmax
Notes:
1.8 0.8 150 300 450 250 800 300 1000 400
ns ns ps ps MHz MHz MHz
Rise/Fall Time Output Pin to Pin Skew (Same Package) Output Skew (Different Package) Input Frequency Input Frequency Input Frequency
1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz
Test Circuit
Vcc
50
Pulse Generator
V+ VV+ V-
D.U.T
50
15pF to 2pF
3
Copyright (c) Potato Semiconductor Corporation
PO100HSTL179A Differential LVDS/LVPECL/HSTL to LVTTL Translator LVTTL/LVCMOS to Differential HSTL Translator
04/26/09
Test Waveforms
FIGURE 1. LVDS/ PECL/ ECL/ HSTL /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS
VCC VCC= 3.3V VIH VPP VIL VEE=0.0V VEE VPP RANGE 0V-VCC
FIGURE 2. LVTTL OUTPUT
tr,tf,
VO
FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for D to output
INPUT CLOCK
TPLH TPD
VPP
TPHL VO
OUTPUT CLOCK
tSK(O)
ANOTHER OUTPUT CLOCK
4
Copyright (c) Potato Semiconductor Corporation
PO100HSTL179A Differential LVDS/LVPECL/HSTL to LVTTL Translator LVTTL/LVCMOS to Differential HSTL Translator
04/26/09
Driver Switching Characteristics
Symbol Description
Propagation Delay D to Output pair Rise/Fall Time Output Pin to Pin Skew (Same Package) Output Skew (Different Package) Input Frequency Input Frequency
Test Conditions (1)
CL = 15pF 0.8V - 2.0V CL = 15pF, 125MHz CL = 15pF, 125MHz CL =15pF CL = 5pF
Typ
M ax
Unit
tPD tr/tf tsk(o) tsk(pp) fmax fmax
Notes:
1.4 0.8 100 250 500 250 1.65 300
ns ns ps ps MHz GHz
1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz
Test Circuit
Vcc
15pF to 2pF
Pulse Generator
D.U.T
50
15pF to 2pF
5
Copyright (c) Potato Semiconductor Corporation
PO100HSTL179A Differential LVDS/LVPECL/HSTL to LVTTL Translator LVTTL/LVCMOS to Differential HSTL Translator
04/26/09
Test Waveforms
FIGURE 1. LVTTL/LVCMOS INPUT WAVEFORM DEFINITION
3V
Input
1.5V 0V
FIGURE 2. HSTL OUTPUT
tr,tf, 20-80%
VO
FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for D to output pair
INPUT CLOCK
TPLH TPD
TPHL VO
OUTPUT CLOCK
tSK(O)
ANOTHER OUTPUT CLOCK
6
Copyright (c) Potato Semiconductor Corporation
PO100HSTL179A Differential LVDS/LVPECL/HSTL to LVTTL Translator LVTTL/LVCMOS to Differential HSTL Translator
04/26/09
Packaging Mechanical Drawing: 8 pin SOIC
8 .0099 .0196 0.25 x 45 0.50 0-8
.149 .157
3.78 3.99
.016 .050 0.40 1.27
.2284 .2440 5.80 6.20
1 .189 .196 .016 .026 0.406 0.660 REF .050 BSC 1.27 .013 0.330 .020 0.508 .0040 0.10 .0098 0.25
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
4.80 5.00 .053 .068 1.35 1.75 SEATING PLANE
.0075 .0098
0.19 0.25
7
Copyright (c) Potato Semiconductor Corporation
PO100HSTL179A Differential LVDS/LVPECL/HSTL to LVTTL Translator LVTTL/LVCMOS to Differential HSTL Translator
04/26/09
Ordering Information
Ordering Code
PO100HSTL179ASU PO100HSTL179ASR 8 pin SOIC 8 pin SOIC
Package
Tube Tape and reel Pb-free & Green Pb-free & Green
Top-Marking
PO100HSTL179AS PO100HSTL179AS
TA -40C to 85C -40C to 85C
IC Package Information
PACKAGE CODE PACKAGE TYPE TAPE WIDTH (mm) TAPE PITCH (mm) PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH QTY PER TUBE
S
SOIC 8
12
8
Top Left Corner
39 (12")
3000
64 (20")
97
8
Copyright (c) Potato Semiconductor Corporation

▲Up To Search▲

Price & Availability of PO100HSTL179A

	To Download PO100HSTL179A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .